1. Field of the Invention
The present invention generally relates to integrated circuit (IC) chips and devices, and more particularly, the present invention relates to solder bump structures of IC chips and devices, and to methods of forming solder bump structures.
2. Description of the Related Art
As integrated circuits (IC's) advance toward higher speeds and larger pin counts, first-level interconnection techniques employing wire bonding technologies have approached or even reached their limits. New improved technologies for achieving fine-pitch wire bonding structures cannot keep pace with the demand resulting from increased IC chip processing speeds and higher IC chip pin counts. As such, the current trend is to replace wire bonding structures with other package structures, such as a flip chip packages and a wafer level packages (WLP).
Flip chip packages and WLP structures are partially characterized by the provision of solder bumps which connect to interconnection terminals of the IC chip. (Herein, unless otherwise specified, the term solder “bumps” is intended to encompass solder “balls” as well.) Device reliability is thus largely dependent on the structure and material of each solder bump and its effectiveness as an electrical interconnect.
A conventional solder bump structure will be described with reference to FIGS. 1 and 2, where like elements are designated by the same reference numbers. FIG. 1 shows the state of a flip chip package prior to mounting on a printed circuit board (PCB) substrate, and FIG. 2 shows the flip chip package mounted on the PCB substrate.
In FIGS. 1 and 2, an integrated circuit (IC) chip 1 is equipped with a chip pad 2, which is typically formed of aluminum. An opening is defined in one or more passivation layers 3 and 4 which expose a surface of the chip pad 2. Interposed between a solder bump 5 and the chip pad 2 are one or more under bump metallurgy (UBM) layers 6 and 7.
The UBM layers 6 and 7 functions to reliably secure the bump 5 to the chip pad 2, and to prevent moisture absorption into chip pad 2 and IC chip 1. Typically, the first UBM layer 6 functions as an adhesion layer and is deposited by sputtering of Cr, Ti, or TiW. Also typically, the second UBM layer 7 functions as a wetting layer and is deposited by sputtering of Cu, Ni, NiV. Optionally, a third oxidation protection layer of Au may be deposited as well.
Referring to FIG. 2, the solder bump 5 is mounted to a PCB pad 8 of a PCB substrate 9.
Mechanical stresses on the solder bump are a source of structural which can substantially impair device reliability. That is, when the chip heats up during use, both the chip and the PCB expand in size. Conversely, when the chip cools during an idle state, both the chip and the PCB substrate contract in size. The chip and the PCB substrate have mismatched coefficients of thermal expansion, and therefore expand and contract at different rates, thus placing mechanical stress on the intervening solder bump. FIG. 3 illustrates a number of examples in which stresses have caused fissures to be formed in the solder bumps. In this figure, reference number 2 denotes a chip pad, reference number 5 denotes the solder bump, reference number 8 denotes the PCB pad, and reference number 10 denotes a crack or fissure. The larger the crack, the more the interconnection becomes impaired, and device failures can occur when cracks propagate completely through the solder bump structure.